1. Field of the Invention
The present invention relates to a pen input apparatus and a pen input method used in input for a personal computer, a word processor, and the like. More particularly, the present invention relates to a pen input apparatus and a pen input method for entering hand written characters and graphic symbols on a tablet provided at the display screen of a display.
2. Description of the Background Art
Referring to FIG. 1, a conventional pen input apparatus includes a liquid crystal panel 101, a back light 102, a detection pen 103, an amplifier 104 for amplifying induced voltage generated at detection pen 103, an inversion signal generation circuit 105 for generating a signal to invert the apply direction of a voltage applied to liquid crystal panel 101, a gate signal generation circuit 107 for generating first and second gate signals in synchronization with the inversion signal, a full-wave rectifier circuit 108 including a diode bridge and the like, a first processing circuit 109 for entering and integrating a signal from full-wave rectifier circuit 108 according to the first gate signal, a second processing circuit for entering and integrating a signal from full-wave rectifier circuit 108 according to the second gate signal, and a comparator circuit 114. First processing circuit 109 includes an analog gate circuit 109a and an integration circuit 109b. Second processing circuit 110 includes an analog gate circuit 110a and an integration circuit 110b.
For the purpose of preventing degradation of the liquid crystal of liquid crystal panel 101 due to electrolysis, the apply direction of the voltage applied to the liquid crystal is inverted periodically according to the level of the inversion signal generated by inversion signal generation circuit 105. At this inversion, the voltage of the drive signals applied to the electrodes of liquid crystal panel 101 are all altered. If detection pen 103 is in the proximity of the surface of liquid crystal panel 101 when the apply direction of the voltage to the electrode of liquid crystal panel 101 is inverted, a spike voltage is induced depending upon the distance between the leading electrode of detection pen 103 and the electrode of liquid crystal panel 101.
Determination can be made that detection pen 103 is in the proximity of liquid crystal panel 101 when the spike induced voltage is greater than a predetermined level. Also, determination can be made that detection pen 103 is remote from liquid crystal panel 101 when the spike induced voltage is below a predetermined level.
FIG. 2 shows in detail first and second processing circuits 109 and 110, and comparator circuit 114 of FIG. 1. First analog gate circuit 109a is formed of a FET (Field Effect Transistor) and the like that is turned on and off when a first gate signal gl generated by gate signal generation circuit 107 attains a high level and a low level, respectively. Similarly, second analog gate circuit 110a is formed of a FET and the like that is turned on and off when a second gate signal g2 generated by gate signal generation circuit 107 attains a high level and a low level, respectively.
Integration circuit 109b includes an operational amplifier 115, a capacitor C1, and a resistor R1. Integration circuit 110b includes an operational amplifier 116, a capacitor C2, and a resistor R2. An integration circuit superior in the S/N ratio can be obtained by setting an appropriate value for the time constant by capacitor C1 and resistor R1, or by capacitor C2 and resistor R2. Comparator circuit 114 includes an operational amplifier 117 to compare the levels of the output voltages of integration circuits 109b and 110b, whereby a detection mode signal pm1 is output attaining a high level when the output of integration circuit 109b has a higher voltage level and a low level when the output of integration circuit 109b has a lower voltage level.
FIGS. 3(A)-(O) is the timing chart of various signals of each component of the pen input apparatus of FIG. 1. Inversion signal generation circuit 105 provides an inversion signal as for inverting the apply direction of the voltage to the electrode of liquid crystal panel 101 to liquid crystal panel 101 and gate signal generation circuit 107. Gate signal generation circuit 107 generates and outputs first and second gate signals g1 and g2 in synchronization with the entered inversion signal as.
Amplifier 104 amplifies the spike induced voltage generated by inversion of the direction of the applied voltage to liquid crystal panel 101 when detection pen 103 is in the proximity of liquid crystal panel 101. The amplified voltage is output as a signal sk. Full-wave rectifier circuit 108 rectifies signal sk and outputs the rectified signal.
First analog gate circuit 109a samples an output signal of full-wave rectifier circuit 108 by first gate signal g1 to output a signal sp1. More specifically, first analog gate circuit 109a is turned on when first gate signal g1 attains a high level, whereby a signal from full-wave rectifier circuit 108 is output. When first gate signal g1 attains a low level, first analog gate circuit 109a is turned off. Similarly, second analog gate circuit 110a samples an output signal of full-wave rectifier circuit 108 according to second gate signal g2 to output a signal sp2.
Integration circuit 109b integrates signal sp1 to output a direct-current voltage dv1. Similarly, integration circuit 110b integrates signal sp2 to output a direct-current voltage dv2. Comparator circuit 114 compares direct-current voltages dv1 and dv2 to provide a detection mode signal pm1 of a high level and a low level when voltage dv1 has a higher and lower level, respectively, than voltage dv2.
However, a noise signal ns that is generated periodically is sampled by analog gate circuit 110a (signal sp4), whereby the voltage level of signal dv4 integrated by integration circuit 110b is increased. There is a possibility that output voltage dv3 from integration circuit 109b does not become higher than output voltage dv4 from integration circuit 110b so that detection mode signal pm2 output from comparator circuit 114 remains at the low level even though detection pen 103 is in the proximity of liquid crystal panel 101. There is a problem that approach of detection pen 103 to liquid crystal panel 101 cannot be properly detected.
Japanese Patent Laying-Open No. 5-265650 discloses a display integrated type tablet apparatus that prevents erroneous detection of the coordinates from the detection pen due to noise by detecting only induced voltage that is generated in response to inversion of the direction of the applied voltage to the liquid crystal when the detection pen approaches the liquid crystal panel.
FIG. 4 is a block diagram showing a structure of this display integrated type tablet apparatus. The display integrated type tablet apparatus includes a detection pen 208, an operational amplifier 209 connected to a leading electrode of detection pen 208, an analog gate AGt for coordinate-detection, analog gates AG.sub.1 and AG.sub.2 for detecting induced voltage, an x-coordinate detection circuit 210 for detecting the x-coordinate, a y-coordinate detection circuit 211 for detecting the y-coordinate, a first processing circuit 223 for rectifying an induced voltage signal sampled by first analog gate AG.sub.1 to obtain an average voltage, a second processing circuit 224 for rectifying an induced voltage signal sampled by second analog gate AG.sub.2 to obtain an average voltage, a first comparator 225 for comparing an average voltage obtained by first processing circuit 223 with a reference value, a second comparator 226 for comparing an average voltage obtained by second processing circuit 224 with a reference value, an AND gate 227, and a coordinate output sorting circuit 228 for discriminating and providing the x-coordinate and the y-coordinate.
The operation of the display integrated type tablet apparatus of FIG. 4 will be described hereinafter while appropriately referring to the timing chart of FIG. 5. An inversion signal for inverting the direction of the applied voltage to the liquid crystal is generated from a clock signal cplo. Gate signal g.sub.1 provides a pulse of a width tg.sub.1 at the transition of inversion signal fro. Gate signal g.sub.2 attains a low level when gate signal g.sub.1 is high, and is driven to a high level at an elapse of a time td from the fall of gate signal g.sub.1.
A spike induced voltage signal E.sub.1 indicates the induced voltage generated by inversion of the direction of the applied voltage to the liquid crystal when detection pen 208 is in the proximity of the liquid crystal panel. Spike induced voltage signal E.sub.1 of one frame period sampled by first analog gate AG.sub.1 is rectified by first processing circuit 223 (signal E.sub.1 g.sub.1) and integrated. First comparator 225 provides a signal of a high level when this integrated voltage value is greater than a reference value.
An induced voltage signal arising from the noise of one frame period sampled by second analog gate AG.sub.2 is rectified by second processing circuit 224 and integrated. Second comparator 226 provides a signal of a high level when this integrated voltage value is smaller than a reference value.
AND gate 227 provides a mode signal of a high level only when the tip of detection pen 208 is close to the liquid crystal panel and the noise is small. Determination is made whether detection of the coordinates is carried out according to this mode signal.
When the noise becomes so great that the integrated voltage value of the induced voltage signal arising from the noise becomes greater than the reference value compared in second comparator 226, there is a problem that detection of the coordinates cannot be carried out.